1. Field of the Invention
The invention relates to a method of fabricating self-aligned silicide (salicide), and more particularly to a method of fabricating salicide for reducing the effect of stress.
2. Description of the Related Art
As the device integration increases, the source/drain region resistance of a MOS device gradually rises until it is equal to the electrons in the tunnel of the MOS. To reduce the sheet resistance in the source/drain region and retain the integrity of a shallow junction of metal and MOS, salicide is accordingly applied in the process.
FIGS. 1A-1D shows a prior art fabricating method for a gate using titanium silicide as salicide. First, as shown in FIG. 1A, a gate oxide layer 102 and a polysilicon layer 104 are formed on the substrate 100. The polysilicon layer 104 and the gate oxide layer 102 are patterned to form a gate structure by photolithography. An ion implantation is next performed on the substrate 100 and a source/drain region 108 is formed therein. An insulating spacer 110 is formed on the sidewalls of the polysilicon layer 104. As shown in FIG. 1A, a layer of titanium 112 is formed over the substrate 100 by RF sputtering. Then, a thermal process is performed to make titanium 112 react with poly gate structure 104 and the source/drain region 108. A salicide 114 is therefore formed on the substrate 100, as shown in FIG. 1B.
In the salicide process described above, the silicide is formed on the source, drain and gate to simplify the step of photolithography and reduce contact resistance. The silicide used in ULSI (Ultra large Scale Integration) is C54-TiSi.sub.2 because it has the lowest resistance, the lowest contact resistance and better thermal conductivity. However, as the dimension of devices shrinks to under 0.25 .mu.m, relational stress problems become serious enough to affect fabrication of the device, the gate oxide layer of a MOSFET becomes worse and defects are induced in interconnect lines by stress.
Using titanium to serve as a metal layer of silicide, silicon atoms migrate into the titanium layer as the silicide is formed and a kind of compressive stress is therefore produced in silicide. The appearance of compressive stress inhibits migration of silicon atoms through a Ti/Si interface and hence the formation of TiSi.sub.2 is retarded. In addition, the growth rate and the maximum thickness of TiSi.sub.2 film is reduced and the film can't be formed continuously. It is also difficult to transfer silicide from C49-TiSi2 to C54-TiSi2 due to compressive stress and it even reduces conductivity of titanium silicide.
Moreover, to relieve the stress between the interfaces, an additional, thinner interlayer, such as molybdenum (Mo) or tungsten (W), is sputtered on the interface. But the interlayer produces defects in the silicide film and the impedance is therefore increased. So this it is not a preferable method of diminishing the stress of the interface.